`timescale 1ns/1ps

module uart_tx_tb();

  reg Clk;
  reg Reset_n;
  reg [7:0] Data;
  reg send_go;
  wire uart_tx;
  wire tx_done;

  // Instantiate the UART transmitter module
  uart_tx uart_tx_inst0 (
    .Clk(Clk),
    .Reset_n(Reset_n),
    .Data(Data),
    .send_go(send_go),
    .uart_tx(uart_tx),
    .tx_done(tx_done)
  );

  // Clock generation: 50 MHz (20ns period)
  always #10 Clk = ~Clk;

  // Initial conditions and stimulus
  initial begin
    // Initialize signals
    Clk = 0;
    Reset_n = 0;
    Data = 8'b0;
    send_go = 0;

    // Reset the system
    #100;
    Reset_n = 1;

    // Test Case 1: Send a byte of data (0x55)
    #100;
    Data = 8'h55;    // Set data to transmit
    send_go = 1;     // Trigger transmission
    #20;
    send_go = 0;     // De-assert send_go after one cycle

    // Wait for transmission to finish
    wait(tx_done);
    #100;

    // Test Case 2: Send a different byte of data (0xA3)
    Data = 8'hA3;    // Set new data to transmit
    send_go = 1;     // Trigger transmission
    #20;
    send_go = 0;     // De-assert send_go after one cycle

    // Wait for transmission to finish
    wait(tx_done);
    #100;

    // End of simulation
    $finish;
  end

endmodule
